The Nano-1 Processor

The Nano-1 processor consists of a control unit and a data path.

Here's a sketch of the Nano-1 data path:

The data path has eight 16-bit registers connected by three 16-bit buses: bus-0, bus-1, and bus-2.

The data path has a 16-bit ALU capable of performing 8 operations:

0. add

1. multiply

2. subtract

3. divide

4. lshift

5. rshift

6. bitwise conjunction

7. complement

The control unit has an 9-bit instruction register (IR).

The format of the IR is: 0uvw where u = OPCODE, v = ARG-0, w = ARG-1. (Note that u, v, and w are 3-bit quantities (i.e. octal digits).

The ARG-0 field tells which register to load onto bus-0. The ARG-1 field tells which register to load onto bus-1. Both of these buses feed into the ALU. The result of the ALU is connected to bus-3. This bus sends its data back into the register selected by ARG-0.

The OPCODE field tells the ALU which operation to perform.

The ALU also has a 16 bit status word that tells carry-out, borrow-out, remainder, or the bit shifted out, depending on OPCODE.

A clock should control the loading of busses and registers.

Users should be able to enter a value into IR, then send clock pulses to route the data from registers into the ALU and back to the registers.

Use Logisim to build a Nano-1 data path. The IR should be a 16 bit input.