Here is a list of my publications.  Several papers were written with my Master’s Thesis Students.




      "Fault-Tolerance Characteristics of Neural Networks", August 1989

The reliability of neural networks implemented in VLSI was investigated using empirical methods.  A fault simulation program was developed to model the effects of typical VLSI failure modes upon the operation of various neural network architectures.  Quantitative measures of a neural network's sensitivity towards VLSI defects is discussed.  A technique to improve the reliability and robustness of neural networks is also presented.




Fort, Randy and Chun, Robert.  “A Comparative Xeon and CBE Performance Analysis”, Proceedings of the 2008 Intl. Conference on Parallel and Distributed Processing Techniques and Applications (Las Vegas, NV, 14-18 July 2008).

The Intel Xeon and Cell Broadband Engine Processors are compared from the perspectives of pipelining, memory accessing, and branching when executing various programmatic structures. 


Frank, Joel and Chun, Robert.  “Adaptive Software Transactional Memory: A Dynamic Approach to Contention Management”, Proceedings of the 2008 Intl. Conference on Parallel and Distributed Processing Techniques and Applications (Las Vegas, NV, 14-18 July 2008).

A dynamic, adaptive technique for contention management is presented. Results show that it yields a higher and more consistent performance level than non-adaptive techniques. 


Cho, Alvin and Chun, Robert.  “Emotion & Domain Concept Enhancements to Alicebot”, Proceedings of the 2007 Intl. Conference on Artificial Intelligence (Las Vegas, NV, 25-28 June 2007).

An emotion and personality model is added to Alicebot so that it can make decisions about what it likes or does not like based on its domain concept preferences.  Alicebot is also augmented with the ability to generate its own text by retrieving current and relevant news reports from the Internet.


Gefter, Denis and Chun, Robert.  “EJB Performance Measurement Framework”, Proceedings of the 2006 Intl. Conference on Software Engineering Research and Practice (Las Vegas, NV, 26-29 June 2006) vol. 1, pp. 303-309 (2006)

A non-intrusive, low-overhead Measurement Framework for profiling the performance of an Enterprise Java Bean based system in a production environment is described.


Hoang, Phuong and Chun, Robert.  “Dynamic Cluster”, Proceedings of the 2006 International Conference on Parallel and Distributed Processing Techniques and Applications (Las Vegas, NV, 26-29 June 2006) volume 2, pp. 744-750 (2006)

A cluster of computers connected together over a wired and wireless network is demonstrated.  Task assignments are automatically redistributed according to the dynamic entry and exit of nodes.


Nguyen, Paul and Chun, Robert.  “Model Driven Development with Interactive Use Cases and UML Models”, Proc. 2006 Intl. Conf. on Software Engineering Research and Practice (Las Vegas, NV, 26-29 June 2006) vol. 2, pp. 534-540 (2006)

This paper investigates an alternative approach to model driven development using dynamic models developed interactively with existing code, thereby providing better support for the maintenance and evolution of the software.  The approach ensures correlation between models and code.


Nguyen, Tri and Chun, Robert.  “Per-Thread Batch Queues for Multi-threaded Programs”, Proceedings of the 2006 International Conference on Parallel and Distributed Processing Techniques and Applications (Las Vegas, NV, 26-29 June 2006) vol. 1, pp. 562-568 (2006)

A new per-thread batch queue algorithm is described along with experimental results comparing batch and non-batch queues.  The research addresses performance issues that can arise due to excessive context switching or busy-waiting by serializing threads on highly contended resources.


Wang, Ming and Chun, Robert.  “The Intelligent C Language Debugger”, Proceedings of the 2006 International Conference on Software Engineering Research and Practice (Las Vegas, NV, 26-29 June 2006) vol. 2, pp. 688-691 (2006)

A debugger which uses test result information to assist programmers in locating errors in a program is described.  An enhanced static slicing algorithm is developed and employed to display a subset of the program containing only the statements that are relevant to the error condition(s).


Jiva, Azeem and Chun, Robert.  “Compilation Scheduling for the Java Virtual Machine", Proceedings of the 2005 International Conference on Programming Languages and Compilers (Las Vegas, NV, 27-30 June 2005) pp. 187-193 (2005)

A new algorithm for managing a Just-In-Time compiler's queue is described.  Using this compilation scheduling scheme, SwingMark scores executed six percentage points faster than when using the standard JDK 1.4.2.  Other benefits include lower startup times and increased overall performance.  The scheduling technique can be used in JIT compilers such as the HotSpot Java Virtual Machine.


Chun, Robert and Rao, Kamlesh.  "An Interactive Profiler and Parallelizer Toolkit”, Proceedings of the 2004 International Conference on Parallel and Distributed Processing Techniques and Applications (Las Vegas, NV, 21-24 June 2004) vol. III pp. 1223-1229 (2004)

A software toolkit which assists a user in parallelizing sequential code is described.  Time-consuming portions of code are identified using static analysis as opposed to a more expensive dynamic analysis employed by most other techniques.  The tool includes a user-friendly interactive environment that gives feedback to the user regarding the potential bottlenecks in the sequential code.  It is designed to target Fortran programs that use the Message Passing Interface (MPI).


Meyer, Christine and Chun, Robert.  “Wireless Cluster Computing”, Proceedings of the 2004 International Conference on Parallel and Distributed Processing Techniques and Applications (Las Vegas, NV, 21-24 June 2004) vol. III, pp. 1167-1172 (2004)

A framework was developed to create a wireless network of mobile laptop computers for providing parallel processing capabilities.  The wireless network uses IEEE 802.11B cards in ad-hoc mode for communication.  A unique characteristic of a wireless network in comparison with a wired network is that the population and effective bandwidth capabilities of the computing nodes can dynamically change.  Portable computers may move in and out of the cluster’s “center of mass”.  Automatic detection and compensation for these changes is described.  Also, since the inter-processor communication bandwidth between any two nodes is a function of the distance and any radio signal attenuating material between the portable machines, a distribution of tasks is performed based on transmission time as well as other load balancing factors.


Chun, Robert and Yang, Linda.  “Reuse of Firmware Tests in System-On-Chip Design Verification”, Proceedings of the 2003 International Conference on Very Large Scale Integration (Las Vegas, NV, 23-26 June 2003) pp. 70-76 (2003)

An architecture and methodology to facilitate the reuse of Intellectual Property (IP) core firmware tests in the verification of System-on-Chip (SoC) designs is presented.  The technique allows for rapid, automated generation of an integrated system-level test to verify a uniquely configured SoC.  Changes in the SoC design, and therefore system test requirements, can be easily accommodated.  The method draws upon the analogy of device drivers and operating systems.  It is shown that the technique not only improves the reusability of the IP core test sequences, but also reduces the overall run time of the integrated system-level test.  An industrial-grade SoC design was used as a demonstration and evaluation vehicle.


Chun, R.K. and Ho, K.  "Load Balancing of a Heterogeneous Cluster Computer System", Proceedings of the 14th IASTED International Conference on Parallel and Distributed Computing Systems (Cambridge, MA, 4-6 November 2002) pp. 356-361 (2002)

A method to load balance a parallel application across a cluster computer system consisting of heterogeneous processing nodes, each with a potentially different CPU, memory configuration, communication bandwidth, and instantaneous loading factor, is discussed.  The method makes building clusters consisting of a wider variety of processing nodes possible.


      "Software Integration of Real-Time Expert Systems"

      R. K. Chun;  IFAC Journal of Control Engineering Practice, Issue 4(1), January 1996

An invited journal paper after I presented this work at the 1994 International Federation of Automatic Control (IFAC) Conference in Sweden.  The memory space and CPU time penalties associated with the inference mechanisms of present-day rule-based environments is addressed.  A synergistic approach utilizing compilation, compaction, and parallelization of a knowledge base is presented as a solution.  A research prototype tool implementing the approach has achieved a 100X execution speedup along with a 19X memory reduction factor for some knowledge bases.  Portions of this work were granted a U. S. Patent.


      "Software Integration of Real-Time Expert Systems"

      R. K. Chun;  1994 International Federation of Automatic Control Conference

A conference version of the journal paper above emphasizing intelligent control technology.


      "An Environment for the Control and Software Integration of Expert Systems"

      R. K. Chun, B. Perry;  1993 Software Engineering and Knowledge Engineering Conference

A method for integrating rule-based expert systems with procedural code is presented.  A research prototype of a graphically oriented software engineering development environment is described.  The meta-programming environment enables constructs from both the rule-based and procedural-based domains to be seamlessly merged into a single delivered application program.  The environment enables the advantages of each programming domain to be appropriately utilized and facilitates software reuse.


      "Synthesis of Parallel Ada Code from a Knowledge Base of Rules"

      R. Chun, R. Lichota, B. Perry, N. Sabha

      1991 IEEE/ACM Symposium on Parallel and Distributed Processing

A technique and prototype system for automatically detecting parallelism in a knowledge base of rules is discussed.  The results of converting the rules into multi-tasking Ada code and executing it on a parallel processor are documented.  It was discovered that although much parallelism exists in a knowledge base, performance advantages were realized only for large and complex rule clusters due to the overhead associated with Ada's tasking mechanism.


      "Immunization Of Neural Networks Against Hardware Faults"

      R. K. Chun, L. P. McNamee

      1990 IEEE International Symposium On Circuits And Systems

This paper summarizes the results of my dissertation work concerning the fault-tolerance characteristics of neural networks.  A method is proposed for augmenting the Backward Error Propagation (BEP) training algorithm to maximize a neural network's resilience against hardware faults, especially those typically found in VLSI circuitry.  The technique involves deliberately injecting faults (via a fault model and a fault simulation program) into the training patterns such that the neural network's own adaptive capabilities are leveraged to "immunize" it against the faults.


      "VISION: VHDL Induced Schematic Imaging On Net-Lists"

      R. K. Chun, K. J. Chang, L. P. McNamee

      1987 IEEE Design Automation Conference (Best Presentation Award)

The results of a method and prototype system capable of automatically generating schematics from structural VHDL code are presented.  The approach incorporates various place and route algorithms which were augmented with pattern recognition rules.  An interesting aspect of this project was the discovery of the importance of generating schematic diagrams in such a manner that readers of the schematic can quickly identify and grasp the functionality of key circuit blocks.  The talk I gave won Best Technical Presentation.


      "Use Of Artificial Intelligence For Electronic Design"

      R. K. Chun, K. J. Chang, W. J. Lue, L. P. McNamee

      Expo Surface Mount Technology 1988

An overview of the various potential applications of artificial intelligence techniques towards computer-aided-design of electronic circuits is presented.


      "VHDL and Neural Networks"

      R. K. Chun, L. P. McNamee

      1988 VHDL User's Group Meeting

This work demonstrated the use of VHDL as a modeling language to describe the architectural structure and behavior of neural networks.  The simulation was done on one of the first VHDL compilers developed in an effort to benchmark its efficiency.


      "The Super Challenge Of Super Chips"

      E. Tsou, A. M. Gold, J. J. Warecki, R. K. Chun

      TRW Quest Magazine, Summer 1987

The many challenges confronted by designers of wafer-scale integrated circuits along with the custom state-of-the-art design automation software tools developed to assist them in meeting these challenges are discussed.


      "Integration Of VHDL Into TRW's CAD Environment"

      R. K. Chun, D. J. Azaren

      1988 Very High Speed Integrated Circuit Tech Fair

An overview was provided as to the various ways in which VHDL was incorporated into the VHSIC design automation department's software tool suite.



Master’s Thesis Advising


I have served as the Master’s Thesis Advisor for:


·       Paul Nguyen, "Engineering Enterprise Software Systems Interactive UML Models and Aspect-Oriented Middleware", graduated Spring 2006

·       Lenna Slingerland, "Context-Awareness and Usability of Mobile Data Collection Application", graduated Spring 2006

·       Phuong Hoang, "Dynamic Cluster", graduated Fall 2005

·       Cary Stanley, "The REEF: A Web System to Form Charity Connections", graduated Fall 2005

·       Kenneth Ton, "DDFS: A Dynamic Distributed File System", graduated Fall 2005

·       Denis Gefter, "EJB Performance Measurement FrameWork", graduated Spring 2005

·       Tri Nguyen, "Per-Thread Batch Queues", graduated Spring 2005

·       Matthew Thornton, "A New Approach to Authentication in Wireless Computing Clusters", graduated Spring 2005

·       Ming Wang, "The Intelligent C Language Debugger", graduated Spring 2005

·       Meera Belur, "Optimized Scheduling of Jobs Under Memory Constraints", graduated Fall 2004

·       Azeem Jiva, "Compilation Scheduling Policy with the Java HotSpot Virtual Machine", graduated Fall 2004

·       Christine Meyer, "Wireless Cluster Computing", graduated Spring 2004.

·       Charlie Tran, "Organic Molecule Formula to 3-D Model", graduated Spring 2004.

·       Kamlesh Rao, "An Interactive Toolkit that assists in Parallelizing and Profiling of Application Code for Distributed Computing", graduated Fall 2003.

·       Linda Yang, "A Method for Reuse of Firmware Tests in System-On-Chip Design Verification", graduated Fall 2002.

·       Ken Ho, "An Integrated System for Load Balanced Heterogeneous Parallel Cluster Computing", graduated Spring 2002.


I have served on the Master’s Thesis Committee for:

·       David Jamin, "Data Warehouse Design Based on Granular Computing", graduated Spr'06

·       Wing Wong, "Analysis and Detection of Metamorphic Computer Viruses" graduated Spr'06

·       Wallun Chan, "Recognition and Age Prediction with Digital Images of Missing Children", graduated Fall 2005

·       Diana Dong, "Similarity Information Retrieval with Category Clustering", graduated Fall'05

·       Robert Lo, "A Performance Evaluation of Serial ATA", graduated Spring 2005

·       Priya Baliga, "An Automata-Based Intrusion Detection System", graduated Fall 2004

·       Shivani Hashia, "Authentication by Mouse Movements", graduated Fall 2004

·       Julie Nabong, “Stylesheet Translations of SVG to VML”, graduated Spring 2004.

·       Ling Wang, “Algorithmic Study Of Edge-Graceful and Super-Edge-Graceful Labelings”, graduated Fall 2003.

·       Li Liu, “Indexing Techniques for XML Query Optimization”, graduated Spring 2003

·       Xin Chen, “Quantum Threshold Gate Simulator”, graduated Spring 2003.