San Jose State University

Fall 2010 Course Syllabus

CS 247:  Advanced Computer Architecture





                           Detailed analysis of high-performance, fault-tolerant computer systems.  Survey various machine architectures including implementation alternatives for major processor sub-systems.  Pipelined, vector, VLSI, multi-core and dataflow architectures are examined.  Discussion includes data representation, arithmetic logic unit operations and algorithms, rounding algorithms, control unit issuing operation and instruction formats.  Performance measurement and speedup techniques are studied to perform tradeoff analysis and design optimization.  Digital FPGA breadboard labs and programming projects with the VHDL language and an industrial-strength simulation environment will be used to demonstrate computer-aided design and functional verification techniques for digital systems.  A written report and oral presentation on a relevant and approved topic of interest to the student will be required.


Meeting Time:                                                                                                

                           Section 1:  MW  1900-2015  MH225




                           CS 147 and CS 149, or instructor consent.


                           Robert K. Chun

Contact Info:                                                                                                                                       

                           EMAIL:,  PHONE:  (408) 924-5137,  OFFICE:  MH 413

Office Hours:                                                                                                                               

                           Monday 11:30am – 12:30pm, 4:15pm – 4:45pm, 8:15pm – 9:00pm

                           Tuesday 11:45am – 12:15pm

                           Wednesday 1:45pm – 2:15pm, 4:15pm – 4:45pm, 8:15pm – 9:00pm

                           Thursday 11:45am – 12:15pm




                           Required:     Computer Organization and Design: The Hardware/Software Interface, 4th Ed., D. Patterson, 2008, Elsevier Science & Technology Books, ISBN 9780123744937


                           Required:     CS 247 Course Reader, Chun.  Purchase at SJSU Print Shop.


                           Optional:     A VHDL Primer, J. Bhasker, 3rd Ed., 1999, Prentice Hall, ISBN 0130965758





                           Grading consists of two midterms, one final, a written and oral report, and a set of projects (consisting of a combination of written problems and VHDL programming assignments) weighted as follows.  Grading is based on a class curve.  All assignments (especially the oral presentation) must be completed by the student on the due date specified to receive credit for the class.  Late assignments or exams are not accepted.  All students must uphold academic honesty, especially for the required term paper, per university policy detailed at


                                       15%     Midterm Exam 1

                                                   Week 6 (Approximate)


                                       15%     Midterm Exam 2

                                                   Week 12 (Approximate)


                                       30%     Term Paper & Presentations

                                                   Weeks 13-15


                                       30%     Final Exam

                                                   Sec. 1: 12/13/10  19:45-2200



                                       10%     Three HW and VHDL Projects combined

                                                   Due as announced in class

Course Objectives:


  • To quickly review combinatorial and sequential circuit structures and Boolean number representation schemes
  • To help students appreciate how the fundamental mathematical operations such as addition, subtraction, multiplication, and division can be optimized with appropriate number representation, rounding, and digital circuit implementation schemes.
  • To educate students about the tradeoffs between complex instruction set computers (CISC) and reduced instruction set computers (RISC).
  • To discuss non-classical architectures such as parallel processors, multi-core chips, pipelined and VLIW machines which are used to accelerate hardware performance without impacting legacy sequential software programming languages or techniques.
  • To introduce computer-aided design tools and hardware description languages useful to computer architects in performing functional verification and performance measurements of digital systems, and to give students the opportunity to use some real-world tools.
  • To expose students to field programmable gate array chips and give them hands-on experience with using them.
  • To emphasize the importance of fault-tolerant design techniques and examine various methods of error detection and correction such as TMR and Hamming Codes.
  • To help students appreciate how hardware and software (especially the operating system and compilers) must work synergistically together to provide optimum throughput.
  • To allow students to perform an in-depth investigation of an architecture related topic of interest to them and present their findings to their classmates in an oral and written report using a venue similar to that used in formal professional technical conferences.
  • Analyze and perform tradeoffs between the cost, performance, and reliability of alternative computer architectures.


Tentative Schedule:


Lecture              Chapter                      Topic


1-4                 1, 2                              Introduction, VHDL

5-6                 3                                  Data Representation

7-10               3                                  High Speed Arithmetic

11                   Notes                           Rounding

                                                           Midterm Exam

12                   Notes                           Cloud Computing

13-16             6                                  Pipeline & Parallel Processing

17-21             Notes, Readings          Fault-Tolerance

                                                           Midterm Exam

22-28                                                 Term Papers & Presentations

                                                           Final Exam


General University Policies



If you need course adaptations or accommodations because of a disability, or if you need special arrangements in case the building must be evacuated, please inform the instructor as soon as possible.  Presidential Directive 97-03 requires that students with disabilities register with DRC to establish a record of their disability.



Academic integrity is essential to the mission of San José State University.  As such, students are expected to perform their own work (except when collaboration is expressly permitted by the course instructor) without the use of any outside resources.  Students are not permitted to use old tests or quizzes when preparing for exams, nor may they consult with students who have already taken the exam. When practiced, academic integrity ensures that all students are fairly graded.


We all share the obligation to maintain an environment which practices academic integrity.  Violations to the Academic Integrity Policy undermine the educational process and will not be tolerated.  It also demonstrates a lack of respect for oneself, fellow students and the course instructor, and can ruin the university’s reputation and the value of the degrees it offers. Violators of the Academic Integrity Policy will be subject to failing this course and being reported to the Office of Judicial Affairs for disciplinary action which could result in suspension or expulsion from San José State University.



At SJSU, cheating is the act of obtaining or attempting to obtain credit for academic work through the use of any dishonest, deceptive, or fraudulent means. Cheating at SJSU includes but is not limited to:


Copying in part or in whole, from another’s test or other evaluation instrument; Submitting work previously graded in another course unless this has been approved by the course instructor or by departmental policy. Submitting work simultaneously presented in two courses, unless this has been approved by both course instructors or by departmental policy.  Altering or interfering with grading or grading instructions; Sitting for an examination by a surrogate, or as a surrogate; any other act committed by a student in the course of his or her academic work which defrauds or misrepresents, including aiding or abetting in any of the actions defined above.



At SJSU plagiarism is the act of representing the work of another as one’s own (without giving appropriate credit) regardless of how that work was obtained, and submitting it to fulfill academic requirements. Plagiarism at SJSU includes but is not limited to:


The act of incorporating the ideas, words, sentences, paragraphs, or parts thereof, or the specific substances of another’s work, without giving appropriate credit, and representing the product as one’s own work; and representing another’s artistic/scholarly works such as musical compositions, computer programs, photographs, painting, drawing, sculptures, or similar works as one’s own.


Additional Information: