Fall 2010 Course Syllabus
CS 247: Advanced Computer Architecture
Detailed analysis of high-performance, fault-tolerant computer systems. Survey various machine architectures including implementation alternatives for major processor sub-systems. Pipelined, vector, VLSI, multi-core and dataflow architectures are examined. Discussion includes data representation, arithmetic logic unit operations and algorithms, rounding algorithms, control unit issuing operation and instruction formats. Performance measurement and speedup techniques are studied to perform tradeoff analysis and design optimization. Digital FPGA breadboard labs and programming projects with the VHDL language and an industrial-strength simulation environment will be used to demonstrate computer-aided design and functional verification techniques for digital systems. A written report and oral presentation on a relevant and approved topic of interest to the student will be required.
Section 1: MW 1900-2015 MH225
CS 147 and CS 149, or instructor consent.
Robert K. Chun
EMAIL: ProfessorChun@gmail.com, PHONE: (408) 924-5137, OFFICE: MH 413
Monday 11:30am – 12:30pm, 4:15pm – 4:45pm, 8:15pm – 9:00pm
Tuesday 11:45am – 12:15pm
Wednesday 1:45pm – 2:15pm, 4:15pm – 4:45pm, 8:15pm – 9:00pm
Thursday 11:45am – 12:15pm
Required: Computer Organization and Design: The Hardware/Software Interface, 4th Ed., D. Patterson, 2008, Elsevier Science & Technology Books, ISBN 9780123744937
Required: CS 247 Course Reader, Chun. Purchase at SJSU Print Shop.
Optional: A VHDL Primer, J. Bhasker, 3rd Ed., 1999, Prentice Hall, ISBN 0130965758
Grading consists of two midterms, one final, a written and oral report, and a set of projects (consisting of a combination of written problems and VHDL programming assignments) weighted as follows. Grading is based on a class curve. All assignments (especially the oral presentation) must be completed by the student on the due date specified to receive credit for the class. Late assignments or exams are not accepted. All students must uphold academic honesty, especially for the required term paper, per university policy detailed at http://www2.sjsu.edu/senate/f88-10.htm
15% Midterm Exam 1
Week 6 (Approximate)
15% Midterm Exam 2
Week 12 (Approximate)
30% Term Paper & Presentations
30% Final Exam
Sec. 1: 12/13/10 19:45-2200
10% Three HW and VHDL Projects combined
Due as announced in class
Lecture Chapter Topic
1-4 1, 2 Introduction, VHDL
5-6 3 Data Representation
7-10 3 High Speed Arithmetic
11 Notes Rounding
12 Notes Cloud Computing
13-16 6 Pipeline & Parallel Processing
22-28 Term Papers & Presentations
General University Policies
If you need course adaptations or accommodations because of a disability, or if you need special arrangements in case the building must be evacuated, please inform the instructor as soon as possible. Presidential Directive 97-03 requires that students with disabilities register with DRC to establish a record of their disability.
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We all share the
obligation to maintain an environment which practices academic integrity.
Violations to the Academic Integrity Policy undermine the educational process
and will not be tolerated. It also demonstrates a lack of respect for
oneself, fellow students and the course instructor, and can ruin the
university’s reputation and the value of the degrees it offers. Violators of
the Academic Integrity Policy will be subject to failing this course and being
reported to the Office of Judicial Affairs for disciplinary action which could
result in suspension or expulsion from
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