CS 159: Parallel Processing
Spring 2010 Course Syllabus
Description: A combination hardware architecture and software development class focused on multi-threaded, parallel processing algorithms and techniques. Overview of high-performance parallel processing hardware architectures ranging from on-chip Instruction-Level Parallelism to multi-core microprocessor chips to large distributed supercomputing systems including Clusters, Grids, and Clouds. Discussion and hands-on exercises in a broad range of various parallel programming paradigms and languages such as Pthreads, MPI, OpenMP, Map-Reduce Hadoop, CUDA and OpenCL. The class focus will be on understanding the fundamental concepts associated with the design and analysis of parallel processing systems. Special emphasis will be placed on avoiding the unique non-deterministic software defects that can arise in parallel processing systems including race conditions and deadlocks. The class will also provide overview of current parallel software development toolkits including debuggers and performance profilers.
Meeting Time: Section 1: MW 1900-2015 MH223
Prerequisites: CS 146 (CS 147 and CS 149 highly recommended), or instructor consent.
Instructor: Robert K. Chun
Contact Info: EMAIL: ProfessorChun@gmail.com, PHONE: (408) 924-5137, OFFICE: MH 413
Office Hours: MW 15:45 – 17:00 and MW 20:15 – 21:30
Textbooks: Required: Multi-Core Programming, Shameem Akhter and Jason Roberts, 2006, Intel Press, ISBN 0-9764832-4-6
Required: Using OpenMP, Barbara Chapman and Gabriele Jost, 2008, MIT Press, ISBN 978-0-262-53302-7.
Parallel Computing, Ridgway Scott and Terry Clark, 2005,
Grading: Grading consists of two midterms, one final, and a set of projects (consisting of a combination of written problems and programming assignments) weighted as follows. Grading is based on a class curve. All assignments must be completed by the student on the due date specified to receive credit for the class. Late assignments or exams are not accepted. All students must uphold academic integrity per university policy detailed at http://www2.sjsu.edu/senate/f88-10.htm
15% Midterm Exam 1 Week 6 (Approximate)
15% Midterm Exam 2 Week 12 (Approximate)
40% HW and Programming Projects Due as announced in class
30% Final Exam 5/19/10 at 19:45-22:00
Student Learning Outcomes:
Upon successful completion of this course, students should be able to understand:
· The Technical and Business motivation and need for current state-of-the-art computing systems to incorporate Parallel Processing into the Hardware and Software Subsystems.
· The Micro-Hardware Architectural Evolutionary Trends leading to on-chip Instruction-Level Parallelism, and Pipelining, SuperScalar, Multi-Function Unit Parallel Processing.
· The Macro-Hardware Architectural Evolutionary Trends leading to Parallel Processing including Flynn’s Taxonomy and the recent progression in high-performance supercomputing architectures from Clusters to Grids and to Clouds.
· Data dependency analysis and hazards which, along with Amdahl’s Law, limits the amount of practical speedup and scalability that can be achieved with Parallel Processing.
· Design and Analysis Techniques for Parallel Processing Systems including the identification of data vs. task partitioning in algorithms and applications.
· The Different Models for implementing parallelism in Computing Systems such as shared memory and message passing.
· The software challenges associated with Parallel Processing including the difference between concurrent vs. parallel execution models, deadlocks and race conditions.
· A sample of current parallel programming paradigms and languages and be able to write parallel programs using them.
1 - 3 Introduction, Motivation and Overview of Parallel Processing with
an emphasis on the Micro- and Macro-Hardware Evolutionary Trends
leading to Parallelism and the Software Challenges of Parallelism
4 - 6 Hardware Parallel Processing including pipelining and Instruction-Level
7 - 8 Multi-Function Parallelism in Hardware
9 Data dependency analysis and control hazard analysis including RAW,
WAR, WAW, and Branch Prediction
10 Limitations of Hardware-based, Software-transparent ILP
11 - 17 Software Challenges of Parallel Processing including Concurrent vs. Parallel
Execution Models, Amdahl’s Law, Deadlocks, Race Conditions, Semaphores
18 Models of Parallelism such as Shared Memory, Message Passing
19 - 25 Parallel Programming Paradigms including Unix Process Forking, PVM,
MPI, OpenMP, CUDA, OpenCL, Hadoop Map-Reduce.
27 Toolsets for Parallel Program Software Development and Debugging
General University Policies
If you need course adaptations or accommodations because of a disability, or if you need special arrangements in case the building must be evacuated, please inform the instructor as soon as possible. Presidential Directive 97-03 requires that students with disabilities register with DRC to establish a record of their disability.
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