AAL 5 tries to simplify the packet format to get a better bandwidth utilization while still allowing segmentation and reassembly.
The AAL 3/4 type field is reduced to a single bit which if on indicates the last cell of a CS-PDU.
The SEQ, MID, Length, and CRC-10 fields are removed.
Instead, to detect missing cells or out of order cells, the CRC-32 checksum of the last cell in the CS-PDU are used.
Len is length number of bytes of data.
Multiplexing can no longer be done on a cell-by-cell basis as in AAL3/4 as MID is no longer. It still can be done on a per packet basis.
Virtual Paths
In ATM, the 24 bit identifier for virtual circuits is split into two parts: VPI, the virtual path identifier, (8 bits) and VCI, the virtual circuit identifier, (16 bits).
This allows one to create a two level hierarchy of virtual circuits.
For instance, a corporation might have two sites which are at some distance between each other.
The VPI might be used to handle circuit paths over the public switches between these two sites; however, all 24 bits would be used for connections between two hosts within the company.
This reduces the size of the tables that the public switches need to maintain about connections for that company.
Quiz
Which of the following is true about the 802.1Q spec for virtual LANS?
It changes the format of Ethernet frames.
All hosts in a system with virtual LANs need to implement the spec.
All frames in an extended LAN that uses 802.1Q will at least pass by all hosts in the LAN.
ATM Physical Layer
ATM was originally defined with the idea that it would run over a SONET physical layer.
ATM can be run over a variety of other physical layer implementations such as TAXI (what FDDI uses), DSL, and wireless.
For all of these implementations one has to figure out how to do framing.
Recall SONET frames were 810 bytes 9 rows of 90 bytes. The first 3 bytes of each row was called the overhead.
When SONET is used as the physical layer, one of the overhead bytes is used to indicate the start of the ATM cell
For synchronization and error checking, this overhead byte is used in this way for each line of the SONET frame.
The CRC in the ATM header occurs in the 5 byte of the cell. So you can also find the start of a cell by reading 5 bytes and checking if the fifth byte would work as a CRC.
Switch Implementation
We next look at different ways one could actually implement a switch.
The simplest way is to just buy a general purpose computer, equip it with a number
of network interfaces, and have it run the appropriate software.
This is actually a popular way to build experimental switches that implement new routing protocols.
Here is a picture of how such a set-up might look:
How well would such a switch perform?
Workstation as Switch Example
We assume that an interface uses DMA to write the RAM directly.
When a packet is in RAM, the CPU can read its header and determine which
interface the packet should be sent out on.
Each packet thus must cross the I/O bus twice: Once when the incoming interface
writes to RAM; once when it is written to the outgoing interface
The packet must be written to and read from main memory once.
The upper bound on aggregate throughput of such a device is thus
either half the main memory bandwidth or half the I/O bus bandwidth, whichever is less.
As an example, 133MHz, 64-bit wide I/O bus can transmit data at a little over 8Gbps.
Since forwarding involves crossing a bus twice, the actual limit is 4Gbps. This rate is enough to handle
a fair number of 100Mbps Ethernet ports, but couldn't be used as a router in the core of the internet.
More on Workstation Example
When packets are short, the cost of processing each packet can be more important than the cost
of merely moving the data.
For instance, suppose that a work station can perform all the tasks to switch a million packets per second (pps).
If each packet is short, say 64 bytes, this implies:
So 512 Mbps, a lot less than the earlier upper bound.
This figure is actually shared by all users connected to the medium. So a 10-port switch would only be able to
cope with an average data rate of 51.2Mbps.
Hardware designers have come up with a large array of switch designs that reduce the amount of contention and provide
high aggregate throughput.
A Basic Switch
The above is a schematic for the common components of a switch:
A control processor in charge of the whole switch. It typically communicates either with the ports directly or with the Switch Fabric
A number of input ports
A number of output ports
A fabric
A port contains things like fiber-optic receivers and lasers, buffers to hold packets that are waiting to be switched or transmitted, etc.
The fabric has the job when presented with a packet on a given input port to deliver that packet to the correct output port.
Ports
One of the roles of the ports is to try to keep the job of the switching fabric as simple and fast as possible.
For instance, if the switch supports a virtual circuit model, then the circuit mapping tables are typically located in the ports.
A port maintains a list of which VCIs are currently in use together with information on what output port a packet should be sent out on for each VCI.
The ports of an Ethernet Switch store tables that map between Ethernet addresses and Output ports (Bridge Forwarding tables).
By the time a packet is handed from an input port to the fabric, the port has typically figured out where it needs to go.
This information is typically either added to the packets or communicated to the fabric with some auxiliary control information.
Next day, we will look a little more at ports, discuss fabrics, and start look at IP.
