Finish Cell Switching; Switch Implementation

CS158a

Chris Pollett

Mar. 9, 2011

Outline

ATM Adaptation Layers
Virtual Paths
ATM Physical Layer
Switch Implementation and Performance

ATM CS-PDU and Cell format for AAL5

ATM AAL5 packet format
< 64KB	0-47 bytes	16 bits	16 bits	32
Data	Pad	Reserved	Len	CRC-32

AAL 5 tries to simplify the packet format to get a better bandwidth utilization while still allowing segmentation and reassembly.
The AAL 3/4 type field is reduced to a single bit which if on indicates the last cell of a CS-PDU.
The SEQ, MID, Length, and CRC-10 fields are removed.
Instead, to detect missing cells or out of order cells, the CRC-32 checksum of the last cell in the CS-PDU are used.
Len is length number of bytes of data.
Multiplexing can no longer be done on a cell-by-cell basis as in AAL3/4 as MID is no longer. It still can be done on a per packet basis.

Virtual Paths

In ATM, the 24 bit identifier for virtual circuits is split into two parts: VPI, the virtual path identifier, (8 bits) and VCI, the virtual circuit identifier, (16 bits).
This allows one to create a two level hierarchy of virtual circuits.
For instance, a corporation might have two sites which are at some distance between each other.
The VPI might be used to handle circuit paths over the public switches between these two sites; however, all 24 bits would be used for connections between two hosts within the company.
This reduces the size of the tables that the public switches need to maintain about connections for that company.

ATM Physical Layer

ATM was originally defined with the idea that it would run over a SONET physical layer.
ATM can be run over a variety of other physical layer implementations such as TAXI (what FDDI uses), DSL, and wireless.
For all of these implementations one has to figure out how to do framing.
Recall SONET frames were 810 bytes 9 rows of 90 bytes. The first 3 bytes of each row was called the overhead.
When SONET is used as the physical layer, one of the overhead bytes is used to indicate the start of the ATM cell
For synchronization and error checking, this overhead byte is used in this way for each line of the SONET frame.
The CRC in the ATM header occurs in the 5 byte of the cell. So you can also find the start of a cell by reading 5 bytes and checking if the fifth byte would work as a CRC.

Drawbacks to ATM

When ATM first came out it was pushed as a replacement for Ethernet as a faster LAN technology.
However, as initially specified it was hard to support broadcast and multicast in ATM, on the other hand this was easy for Ethernet.
Broadcast and multi-cast capabilities are more important than you might think because several important internet protocols like ARP rely on them.
Ethernet speeds then quickly caught up with those of ATM, making ATMs speed advantage irrelevant.
Eventually, a spec for LAN ATM (LANE) was developed but it was too little too late.

Switch Implementation

We next look at different ways one could actually implement a switch.
The simplest way is to just buy a general purpose computer, equip it with a number of network interfaces, and have it run the appropriate software.
This is actually a popular way to build experimental switches that implement new routing protocols.
Here is a picture of how such a set-up might look:
How well would such a switch perform?

Workstation as Switch Example

We assume that an interface uses DMA to write the RAM directly.
When a packet is in RAM, the CPU can read its header and determine which interface the packet should be sent out on.
Each packet thus must cross the I/O bus twice: Once when the incoming interface writes to RAM; once when it is written to the outgoing interface
The packet must be written to and read from main memory once.
The upper bound on aggregate throughput of such a device is thus either half the main memory bandwidth or half the I/O bus bandwidth, whichever is less.
As an example, 133MHz, 64-bit wide I/O bus can transmit data at a little over 8Gbps.
Since forwarding involves crossing a bus twice, the actual limit is 4Gbps. This rate is enough to handle a fair number of 100Mbps Ethernet ports, but couldn't be used as a router in the core of the internet.

More on Workstation Example

When packets are short, the cost of processing each packet can be more important than the cost of merely moving the data.
For instance, suppose that a work station can perform all the tasks to switch a million packets per second (pps).
If each packet is short, say 64 bytes, this implies:
```
Throughput = pps × (BitsPerPacket)
           = 1 × 10^6 × 64 × 8
           = 512 × 10^6
```
So 512 Mbps, a lot less than the earlier upper bound.
This figure is actually shared by all users connected to the medium. So a 10-port switch would only be able to cope with an average data rate of 51.2Mbps.
Hardware designers have come up with a large array of switch designs that reduce the amount of contention and provide high aggregate throughput.

A Basic Switch

The above is a schematic for the common components of a switch:
1. A control processor in charge of the whole switch. It typically communicates either with the ports directly or with the Switch Fabric
2. A number of input ports
3. A number of output ports
4. A fabric
A port contains things like fiber-optic receivers and lasers, buffers to hold packets that are waiting to be switched or transmitted, etc.
The fabric has the job when presented with a packet on a given input port to deliver that packet to the correct output port.

Ports

One of the roles of the ports is to try to keep the job of the switching fabric as simple and fast as possible.
For instance, if the switch supports a virtual circuit model, then the circuit mapping tables are typically located in the ports.
A port maintains a list of which VCIs are currently in use together with information on what output port a packet should be sent out on for each VCI.
The ports of an Ethernet Switch store tables that map between Ethernet addresses and Output ports (Bridge Forwarding tables).
By the time a packet is handed from an input port to the fabric, the port has typically figured out where it needs to go.
This information is typically either added to the packets or communicated to the fabric with some auxiliary control information.

Ports and Performance

We said we wanted to minimize the calculations the fabric does to make it as fast as possible.
So input ports maintain things like bridge tables and given an input packet can calculate which output port it should go to.
The correct output port might be either added to the packet (self-routing) or provided as auxiliary info to the fabric. It is the fabrics job to get it to the correct output port.
The input port is thus a source of potential bottlenecks. Depending on the switch, the input port may only have to do a table look up or it might have to do complicated pattern matching and calculations on the header of the packet.
As an example of how fast a switch might need to operate consider a OC-48 link (2.48Gbps) into a switch port.
Such a port needs to process 64 byte packets at a rate of 2.48 × 10⁹ ÷ (64 × 8) = 4.83 × 10⁶pps.
So it has 200ns to figure out which output port a given packet goes to.

Buffering Bottlenecks

Ports (either input or output) also maintain buffers and these can be sources of bottlenecks.
For instance, suppose the buffers are on input ports and are essentially FIFO queues. If several input ports want to send over the fabric packets to the same output port, then only one can send at a time.
This causes packets arriving on the other input ports to queue, even if the output port they are destined to is free.
This phenomena is called head-of-line blocking.
Under a uniform traffic models, head-of-line blocking limits input-buffered switches to 59% of the theoretical maximum throughput.
For this reason, the majority of switches use either pure output port buffering, or a mixture of input and output port buffering.
Buffering is also related to QoS as buffers have a finite length, and packets can get dropped due to lack of space on them.

Fabrics

A considerable amount of research has been done in trying to make fabrics as fast as possible.
A typical high-performance fabric with n ports can often move one packet from each of its ports to any one of the output ports at the same time.
The following are some common types of fabrics:
- Shared Bus - This is the workstation switch, that we described last day. If used in a high-performance switch then typically a specially designed bus is needed, as bus I/O determines throughput.
- Shared Memory - packets are written into a memory by an input port, then read from this memory by an output post. Memory bandwidth determines the throughput in this case.
- Crossbar - each input port has a line with drop lines to each output port. the particular drop-line that will be used is determined by circuits at each line/drop line connection, and makes use of the destination port number.
- Self-routing - a self routing header is appended to the packet by the input port after the output port has been determined. Then a network of 2 x 2 switching elements is used to guide the packet to the correct output port. An example of a fabric network build from 2x2 elements are so-called batcher-banyan networks.