|
Week |
Date |
Topic |
|
Assignment Due |
|
0 |
8/25/05 |
Introduction & Overview |
1.1 |
|
|
1 |
8/30/05 |
Binary Logic |
2.1-2.3 |
|
|
9/1/05 |
Karnaugh Maps |
2.4-2.5 |
|
|
|
2 |
9/6/05 |
Gates, PLD |
2.6-2.8, 3.6 |
|
|
9/8/05 |
Combinational Functions |
4.1-4.5 |
|
|
|
3 |
9/13/05 |
Sequential Logic I |
6.1-6.3 |
HW 1 |
|
9/15/05 |
Sequential Logic II |
6.4-6.6 |
|
|
|
4 |
9/20/05 |
Review |
|
|
|
9/22/05 |
Midterm 1 |
|
|
|
|
5 |
9/27/05 |
Arithmetic |
5.1-5.4 |
|
|
9/29/05 |
Registers |
7.1-7.6 |
|
|
|
6 |
10/4/05 |
Computer Design Basics I |
10.1-10.3 |
|
|
10/6//05 |
Computer Design Basics II |
10.4-10.6 |
|
|
|
7 |
10/11/05 |
Computer Design Basics III |
10.7-10.10 |
HW 2 |
|
10/13/05 |
Instruction Set Architecture I |
11.1-11.3 |
|
|
|
8 |
10/18/05 |
Instruction Set Architecture II |
11.4-11.6 |
|
|
10/20/05 |
Instruction Set Architecture III |
11.7-11.10 |
|
|
|
9 |
10/25/05 |
Review |
|
|
|
10/27/05 |
Midterm 2 |
|
|
|
|
10 |
11/1/05 |
Single Cycle Control, Datapath |
|
|
|
11/3/05 |
Pipelined Datapath |
12.1-12.2 |
|
|
|
11 |
11/8/05 |
RISC Architecture |
12.3 |
HW 3 |
|
11/10/05 |
CISC Architecture |
12.4-12.6 |
|
|
|
12 |
11/15/05 |
Memory |
14.1 |
|
|
11/17/05 |
Cache |
14.2-14.3 |
|
|
|
13 |
11/22/05 |
Virtual Memory |
14.4 |
|
|
11/24/05 |
None (Thanksgiving) |
|
|
|
|
14 |
11/29/05 |
I/O and Communication |
13.1-13.9 |
HW 4 |
|
12/1/05 |
VHDL, Parallel Architectures |
|
|
|
|
15 |
12/6/05 |
Additional Topics |
|
|
|
12/8/05 |
Review |
|
|